1. Field of the Invention
The present invention relates to electrically programmable and erasable non-volatile memory and integrated circuits including such memory, and more particularly to architectures for such devices supporting multiple algorithms for programming, erasing, and reading such memory.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies, including flash memory, are being adapted to many applications. Technologies based upon floating gates like standard EEPROM, or localized charge trapping structures like oxide-nitride-oxide memory cells known in various architectures as SONOS cells and NROM, are typically programmable and erasable many times. Flash memory technologies can be differentiated according to their use for storing data or code. Thus, market segments for so-called data flash and so-called code flash have developed.
Data flash has several characteristics: (1) high density storage; (2) fast page program speed (for example: 16 k bit per page); (3) fast page read speed. Data flash often is used for mass storage applications, where the data stored may include image files produced using digital cameras, files and directory structures in flash cards, audio files like MP3 files, and files of digital samples from analog signals, and other storage applications in which a majority of the program, erase and read transactions involve patterns of data usage involving relatively large data sets. Three representative memory architectures that can serve the data flash market, include: NAND (Toshiba/Samsung), AG-AND (Renesas) and PHINES (Macronix; see Yeh, et al., PHINES: a Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory Cell, 2002 IEDM, p. 931-934; and U.S. Pat. No. 6,690,601). Among the just listed alternatives, the floating gate based NAND architecture might be considered the current mainstream architecture for data flash.
Code flash has several characteristics, including (1) fast byte (8 bits) program speed; and (2) fast random memory access time for single bit for sensing. Code flash is often used for storage of data like computer instructions and parameters for devices like personal computers and mobile phones, in which a majority of the program, erase and read transactions involve patterns of data usage involving relatively small data sets, like updates to instructions and subroutine segments within computer programs and setting and changing values in parameter sets. Three representative memory architectures that can serve the code flash market, include: NOR (Intel, AMD; see U.S. Pat. No. 6,370,062), DINOR, split-gate and NROM (See, U.S. Pat. No. 5,768,192). Among the just listed alternatives, the floating gate based NOR architecture might be considered the current mainstream architecture for code flash. Although it has been proposed to use NROM memory to store both code and data, the operation algorithm used for NROM is considered more suitable to use as code flash.
In general, data flash and code flash are differentiated by operation algorithms for programming, erasing and reading the data, and by the memory cell structures which are adapted to the operation algorithms. Thus, integration of conventional flash memory technology for both code and data flash purposes has not been practical. Accordingly, much existing technology relies upon two chips, one for code flash and one for data flash, to serve these functions. More recent technology relies upon one chip, with multiple arrays having different memory cell structures, one for code flash and one for data flash, to serve these functions. The cost of systems in terms of space on the board, the number of chips, and difficulty in design is high as a result.
Accordingly, it is desirable to provide systems and methods for providing integrated flash memory on the same memory array of a single chip for both code and data storage.
Another trend in flash memory technologies is the increasing density of data storage. Floating gates like standard EEPROM are generally highly conductive structures and thus each has a single region for storing data. Localized charge trapping structures like oxide-nitride-oxide memory cells, known in various architectures as SONOS cells and NROM, store bits in different parts of the charge trapping structure, and thus each charge trapping structure has multiple regions for storing data. Multi-level cell algorithms associate more than two threshold voltage states to each region for storing data. For example, a multi-level cell algorithm with four threshold voltage state stores two bits in region for storing data a multi-level cell algorithm with eight threshold voltage state stores three bits in region for storing data.
Accordingly, it is desirable to provide systems and methods for providing flash memory with a multi-level cell algorithm supporting higher densities of data storage.